The present invention relates to an assembly of semiconductor chips having photosensors thereon for use in a full-page-width image scanner, such as would be used in, for example, a digital copier.
In a full-page-width image scanner, there is provided a linear array of small photosensors which extends the full width of an original document, such as 11 inches. These photosensors may be spaced as finely as 600 to the inch on each chip. When the original document moves past the linear array, each of the photosensors converts reflected light from the original image into electrical signals. The motion of the original image perpendicular to the linear array causes a sequence of signals to be output from each photosensor, which can be converted into digital data.
A currently-preferred design for creating such a long linear array of photosensors is to provide a set of relatively small semiconductor chips, each semiconductor chip defining thereon a linear array of photosensors along with ancillary circuit devices. These chips are typically approximately 3/4 inches in length; in order to create a practical full-page-width array, as many as twenty or more of these chips can be abutted end-to-end to form a single linear array of photosensors. The abutted chips are typically mounted on a support platform. This support platform also includes circuitry, such as on a printed wire board, which accesses the circuit devices on the individual chips for a practical system. The interconnections between the relatively large-scale conductors on the printed wire board and the relatively small contact pads on the semiconductor chips are preferably created by wire bonds which are ultrasonically welded to both the printed wire board conductors and to contact pads on the chips.
One common design for semiconductor chips is to use the "back plane" of each chip, i.e., the surface of the chip opposite that having the photosensors and the circuitry thereon, as a ground terminal for the circuitry on the chip. It is therefore desirable to electrically access each chip in the set of chips forming the linear array both on the top surface thereof, where the contact pads are typically located, and also on the back plane thereof.
U.S. Pat. No. 4,649,424 discloses a CCD imaging apparatus having an improved signal-to-noise ratio, wherein the CCD chip is grounded on its back plane by two separate ground-plane surfaces.
U.S. Pat. No. 4,954,197 discloses a process for fabricating a full-width array of smaller chips bonded end-to-end onto a substrate by an electrically connective heat activated adhesive.
U.S. Pat. No. 4,976,802 discloses a process for fabricating a full-width scanning or printing array with plural chips bonded end-to-end on a glass substrate using a photocurable adhesive. Once the chips are placed on the substrate, light is transmitted through the substrate in order to cure the adhesive.
U.S. Pat. No. 5,034,083 discloses an extended scanning or printing array having smaller chips bonded end-to-end onto a glass substrate having an opaque coating thereon which is thermally and/or electrically conductive. The coating is removed at discrete sites to allow a photocurable adhesive to be cured through exposure to ultraviolet light transmitted through the substrate.
U.S. Pat. No. 5,311,059 discloses a semiconductor device package comprising a substrate with a metallization pattern on one surface and a semiconductor device having an active surface and a grounded surface on opposed sides. The semiconductor device is attached to the metalization pattern with the active surface thereof facing the substrate. An electrically conductive material covers the exposed grounded surface of the semiconductor device to provide an electrical connection between the grounded surface of the semiconductor and the metalization pattern on the substrate.
U.S. Pat. No. 5,326,414 discloses a circuit carrier assembly including a support structure having a base and surrounding walls forming an internal cavity. A plurality of conductor paths are disposed within the cavity, forming a polymeric cover with wall members integrally fashioned into a surface thereof.